Project Release Information
While the release focus is clearly on bugfixes,
there are also some feature improvements, such as
enhanced test bench support and improved netlist
and simulator views. The VHDL compiler has support
for subprograms now and elaboration of big designs
is much faster because of improved context
handling. Internally, the intermediate
representation layer was cleaned up, so
intermediate objects form a proper tree now.
Besides many bugfixes, this release features an improved Eclipse plugin that includes a new Signs console, autobuilder improvements, and outline view navigation. The VHDL compiler has support for attribute elaboration and VHDL87 style file declarations, and reports precise source locations for netlist annotations and error messages. New features in this release include an experimental Berkeley SIS interface, BLIF netlist output, adder and comparator generation, and better support for test benches.
NAND/NOR tree generation for ISCAS netlists has been fixed, (limited) support for selected signal assignment elaboration has been added, CLA (adder) generation has been fixed, the netlist viewer has additional toolbar buttons to access dump and netlist processing functions from the Eclipse plugin, mouse signal selection has been fixed, and the Ant build script is no longer missing from the source distribution.
This release includes a new JavaCC based VHDL
parser that supports a much bigger VHDL subset
than before. The GUI has been removed and instead
a Signs Eclipse plugin is offered for design entry
and exploration. Furthermore, Signs can dump out
(and quickly read back in) intermediate library
files and netlists. For computer-aided testing,
the ATPG and Faultsim modules have been vastly
This release featured lots of ATPG/Faultsim bugfixes and a much improved netlist viewer, which handles busses correctly. Performance of the handling of large netlists was improved.
Signs is a development environment for hardware