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/*
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* Copyright (c) 2007, 2008 University of Tsukuba
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* 1. Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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* 3. Neither the name of the University of Tsukuba nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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* Copyright (c) 2010-2012 Yuichi Watanabe
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*/
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#include <core/assert.h>
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#include <core/string.h>
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#include <core/mm.h>
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#include <core/printf.h>
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#include "constants.h"
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#include "cpu_mmu.h"
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#include "current.h"
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#include "mm.h"
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#include "msr_pass.h"
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#include "panic.h"
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#define USER_MODE()\
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seg_user_mode();
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struct get_pte_data {
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unsigned int pg : 1; /* PG (Paging): CR0 bit 31 */
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unsigned int wp : 1; /* WP (Write Protect): CR0 bit 16 */
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unsigned int pse : 1; /* PSE (Page Size Extensions): CR4 bit 4 */
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unsigned int pae : 1; /* PAE (Physical Address Extensions):CR4bit5 */
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unsigned int lme : 1; /* LME (Long Mode Enable): MSR(EFER) bit 8 */
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unsigned int nxe : 1; /* NXE (No-Execute Enable):MSR(EFER) bit 10 */
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unsigned int write : 1; /* Write access. Set D bit if 1 */
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unsigned int user : 1; /* User access */
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unsigned int exec : 1; /* Execution */
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};
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static u64 reserved_bit_table[2][3][5] = {
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/* NXE = 0 */
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{
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/* levels = 2 (32-bit, PAE = 0, PSE = 1) */
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{
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0x0000000000200000ULL, /* PDE, 4-MByte page */
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0x0000000000000000ULL, /* PTE */
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0x0000000000000000ULL, /* PDE, 4-KByte page */
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0xFFFFFFFFFFFFFFFFULL, /* PDPTE */
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0xFFFFFFFFFFFFFFFFULL, /* PML4E */
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},
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/* levels = 3 (32-bit, PAE = 1) */
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{
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0xFFFFFF00001FE000ULL, /* PDE, 2-MByte page */
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0xFFFFFF0000000000ULL, /* PTE */
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0xFFFFFF0000000000ULL, /* PDE, 4-KByte page */
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0xFFFFFF00000001E6ULL, /* PDPTE */
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0xFFFFFFFFFFFFFFFFULL, /* PML4E */
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},
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/* levels = 4 (64-bit) */
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{
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0x800FFF00001FE000ULL, /* PDE, 2-MByte page */
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0x800FFF0000000000ULL, /* PTE */
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0x800FFF0000000000ULL, /* PDE, 4-KByte page */
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0x800FFF0000000000ULL, /* PDPTE */
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0x800FFF0000000000ULL, /* PML4E */
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},
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},
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/* NXE = 1 */
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{
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/* levels = 2 (32-bit, PAE = 0, PSE = 1) */
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{
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0x0000000000200000ULL, /* PDE, 4-MByte page */
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0x0000000000000000ULL, /* PTE */
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0x0000000000000000ULL, /* PDE, 4-KByte page */
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0xFFFFFFFFFFFFFFFFULL, /* PDPTE */
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0xFFFFFFFFFFFFFFFFULL, /* PML4E */
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},
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/* levels = 3 (32-bit, PAE = 1) */
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{
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0x7FFFFF00001FE000ULL, /* PDE, 2-MByte page */
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0x7FFFFF0000000000ULL, /* PTE */
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0x7FFFFF0000000000ULL, /* PDE, 4-KByte page */
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0xFFFFFF00000001E6ULL, /* PDPTE */
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0xFFFFFFFFFFFFFFFFULL, /* PML4E */
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},
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/* levels = 4 (64-bit) */
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{
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0x000FFF00001FE000ULL, /* PDE, 2-MByte page */
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0x000FFF0000000000ULL, /* PTE */
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0x000FFF0000000000ULL, /* PDE, 4-KByte page */
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0x000FFF0000000000ULL, /* PDPTE */
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0x000FFF0000000000ULL, /* PML4E */
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},
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},
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};
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static bool
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test_pmap_entry_reserved_bit (u64 entry, int level, int levels,
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struct get_pte_data d)
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{
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u64 mask;
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if (!d.pae && !d.pse) /* PAE = 0, PSE = 0 */
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return false; /* No reserved bits checked */
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if (level == 2 && (entry & PDE_PS_BIT))
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level = 0;
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mask = reserved_bit_table[d.nxe][levels - 2][level];
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ASSERT (mask != 0xFFFFFFFFFFFFFFFFULL);
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if (entry & mask)
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return true;
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return false;
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}
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static bool
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set_ad_bit (pmap_t *m, u64 entry, bool seta, bool setd)
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{
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if (entry & PDE_A_BIT)
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seta = false;
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if (entry & PDE_D_BIT)
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setd = false;
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if (seta || setd) {
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if (seta)
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entry |= PDE_A_BIT;
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if (setd)
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entry |= PDE_D_BIT;
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return pmap_write (m, entry, 0xFFF);
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} else {
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return false;
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}
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}
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/* simplify1: entries[0] & entries[1] are generated when paging is disabled */
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/* simplify2: entries[2] (PDPTE) |= RW|US|A when 32-bit PAE */
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/* simplify3: entries[1] (PDE) &= ~PS when PSE is disabled */
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/* simplify : entries[] are 64-bit when PAE is disabled */
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/* simplify : entries[0] (PTE) will be generated when it is in a large page */
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static vmmerr_t
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get_pte_sub (ulong virt, ulong cr3, struct get_pte_data d, u64 entries[5],
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int *plevels)
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{
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pmap_t m;
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int levels;
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int i;
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u64 entry;
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vmmerr_t r;
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if (!d.pg) {
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/* Paging disabled */
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/* simplify1 */
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entries[0] = (virt & PTE_ADDR_MASK64) | PTE_P_BIT | PTE_RW_BIT
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| PTE_US_BIT | PTE_A_BIT | PTE_D_BIT;
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entries[1] = PDE_P_BIT | PDE_RW_BIT | PDE_US_BIT | PDE_A_BIT
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| PDE_D_BIT | PDE_PS_BIT;
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*plevels = 1;
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return VMMERR_SUCCESS;
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}
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/* Paging enabled */
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if (d.lme) {
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d.pae = 1;
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d.pse = 1;
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levels = 4;
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} else if (d.pae) {
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d.pse = 1;
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levels = 3;
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} else {
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levels = 2;
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}
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*plevels = levels;
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pmap_open_guest (&m, cr3, levels, true);
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pmap_setvirt (&m, virt, levels + 1);
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entry = pmap_read (&m);
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entry |= PDE_RW_BIT | PDE_US_BIT | PDE_A_BIT;
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entries[levels] = entry;
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for (i = levels; i >= 1; i--) {
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pmap_setlevel (&m, i);
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retry:
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entry = pmap_read (&m);
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if (!(entry & PDE_P_BIT))
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goto ret_nopage;
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if (test_pmap_entry_reserved_bit (entry, i, levels, d))
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goto ret_reserved;
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if (levels == 3 && i == 3) /* simplify2 */
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entry |= PDE_RW_BIT | PDE_US_BIT | PDE_A_BIT;
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if (!(entry & PDE_US_BIT) && d.user)
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goto ret_noaccess;
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if (!(entry & PDE_RW_BIT) && d.write && (d.wp || d.user))
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goto ret_noaccess;
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if ((entry & PDE_NX_BIT) && d.exec && d.nxe)
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goto ret_noexec;
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if (i == 2 && !d.pse) /* simplify3 */
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entry &= ~(u64)PDE_PS_BIT;
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if ((i == 2 && (entry & PDE_PS_BIT)) || i == 1) {
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if (set_ad_bit (&m, entry, true, d.write))
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goto retry;
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} else {
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if (set_ad_bit (&m, entry, true, false))
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goto retry;
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}
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entries[i - 1] = entry;
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}
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r = VMMERR_SUCCESS;
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ret:
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pmap_close (&m);
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return r;
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ret_nopage:
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r = VMMERR_PAGE_NOT_PRESENT;
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goto ret;
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ret_reserved:
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r = VMMERR_PAGE_BAD_RESERVED_BIT;
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goto ret;
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ret_noaccess:
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r = VMMERR_PAGE_NOT_ACCESSIBLE;
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goto ret;
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ret_noexec:
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r = VMMERR_PAGE_NOT_EXECUTABLE;
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goto ret;
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}
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vmmerr_t
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mmu_get_pte (ulong virt, ulong cr0, ulong cr3, ulong cr4, u64 efer,
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bool write, bool user, bool exec, u64 entries[5],
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int *plevels)
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{
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struct get_pte_data d;
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d.pg = !!(cr0 & CR0_PG_BIT);
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d.wp = !!(cr0 & CR0_WP_BIT);
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d.pse = !!(cr4 & CR4_PSE_BIT);
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d.pae = !!(cr4 & CR4_PAE_BIT);
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d.lme = !!(efer & MSR_IA32_EFER_LME_BIT);
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d.nxe = !!(efer & MSR_IA32_EFER_NXE_BIT);
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d.write = write;
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d.user = user;
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d.exec = exec;
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return get_pte_sub (virt, cr3, d, entries, plevels);
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}
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static vmmerr_t
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get_pte (ulong virt, bool wr, bool us, bool ex, u64 *pte)
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{
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int levels;
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vmmerr_t r;
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u64 entries[5];
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u64 efer;
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ulong cr0, cr3, cr4;
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current->vmctl.read_control_reg (CONTROL_REG_CR0, &cr0);
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current->vmctl.read_control_reg (CONTROL_REG_CR3, &cr3);
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current->vmctl.read_control_reg (CONTROL_REG_CR4, &cr4);
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current->vmctl.read_msr (MSR_IA32_EFER, &efer);
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r = mmu_get_pte (virt, cr0, cr3, cr4, efer, wr, us, ex, entries,
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&levels);
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| 272 |
if (r == VMMERR_SUCCESS)
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*pte = entries[0];
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return r;
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}
|
| 276 |
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vmmerr_t
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write_linearaddr_b (ulong linear, u8 data)
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| 279 |
{
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| 280 |
u64 pte;
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bool us;
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| 282 |
vmmerr_t err;
|
| 283 |
|
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us = USER_MODE();
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err = get_pte(linear, true, us, false, &pte);
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| 286 |
if (err) {
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| 287 |
mmu_generate_pagefault(err, true, us, linear);
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| 288 |
return err;
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| 289 |
}
|
| 290 |
write_gphys_b((pte & PTE_ADDR_MASK64) | (linear & 0xFFF), data,
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| 291 |
msr_pte_to_cache_flag(pte));
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| 292 |
return VMMERR_SUCCESS;
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| 293 |
}
|
| 294 |
|
| 295 |
vmmerr_t
|
| 296 |
write_linearaddr_w (ulong linear, u16 data)
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| 297 |
{
|
| 298 |
u64 pte;
|
| 299 |
bool us;
|
| 300 |
vmmerr_t err;
|
| 301 |
|
| 302 |
if ((linear & 0xFFF) == 0xFFF) {
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| 303 |
RIE (write_linearaddr_b (linear, data));
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| 304 |
RIE (write_linearaddr_b (linear + 1, data >> 8));
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| 305 |
return VMMERR_SUCCESS;
|
| 306 |
}
|
| 307 |
|
| 308 |
us = USER_MODE();
|
| 309 |
err = get_pte(linear, true, us, false, &pte);
|
| 310 |
if (err) {
|
| 311 |
mmu_generate_pagefault(err, true, us, linear);
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| 312 |
return err;
|
| 313 |
}
|
| 314 |
write_gphys_w ((pte & PTE_ADDR_MASK64) | (linear & 0xFFF), data,
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| 315 |
msr_pte_to_cache_flag(pte));
|
| 316 |
return VMMERR_SUCCESS;
|
| 317 |
}
|
| 318 |
|
| 319 |
vmmerr_t
|
| 320 |
write_linearaddr_l (ulong linear, u32 data)
|
| 321 |
{
|
| 322 |
u64 pte;
|
| 323 |
bool us;
|
| 324 |
vmmerr_t err;
|
| 325 |
|
| 326 |
if ((linear & 0xFFF) >= 0xFFD) {
|
| 327 |
RIE (write_linearaddr_w (linear, data));
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| 328 |
RIE (write_linearaddr_w (linear + 2, data >> 16));
|
| 329 |
return VMMERR_SUCCESS;
|
| 330 |
}
|
| 331 |
us = USER_MODE();
|
| 332 |
err = get_pte(linear, true, us, false, &pte);
|
| 333 |
if (err) {
|
| 334 |
mmu_generate_pagefault(err, true, us, linear);
|
| 335 |
return err;
|
| 336 |
}
|
| 337 |
write_gphys_l ((pte & PTE_ADDR_MASK64) | (linear & 0xFFF), data,
|
| 338 |
msr_pte_to_cache_flag(pte));
|
| 339 |
return VMMERR_SUCCESS;
|
| 340 |
}
|
| 341 |
|
| 342 |
vmmerr_t
|
| 343 |
write_linearaddr_q (ulong linear, u64 data)
|
| 344 |
{
|
| 345 |
u64 pte;
|
| 346 |
bool us;
|
| 347 |
vmmerr_t err;
|
| 348 |
|
| 349 |
if ((linear & 0xFFF) >= 0xFF9) {
|
| 350 |
RIE (write_linearaddr_l (linear, data));
|
| 351 |
RIE (write_linearaddr_l (linear + 4, data >> 32));
|
| 352 |
return VMMERR_SUCCESS;
|
| 353 |
}
|
| 354 |
us = USER_MODE();
|
| 355 |
err = get_pte(linear, true, us, false, &pte);
|
| 356 |
if (err) {
|
| 357 |
mmu_generate_pagefault(err, true, us, linear);
|
| 358 |
return err;
|
| 359 |
}
|
| 360 |
write_gphys_q ((pte & PTE_ADDR_MASK64) | (linear & 0xFFF), data,
|
| 361 |
msr_pte_to_cache_flag(pte));
|
| 362 |
return VMMERR_SUCCESS;
|
| 363 |
}
|
| 364 |
|
| 365 |
vmmerr_t
|
| 366 |
read_linearaddr_b (ulong linear, void *data)
|
| 367 |
{
|
| 368 |
u64 pte;
|
| 369 |
bool us;
|
| 370 |
vmmerr_t err;
|
| 371 |
|
| 372 |
us = USER_MODE();
|
| 373 |
err = get_pte(linear, false, us, false /* FIXME */, &pte);
|
| 374 |
if (err) {
|
| 375 |
mmu_generate_pagefault(err, false, us, linear);
|
| 376 |
return err;
|
| 377 |
}
|
| 378 |
read_gphys_b ((pte & PTE_ADDR_MASK64) | (linear & 0xFFF), data,
|
| 379 |
msr_pte_to_cache_flag(pte));
|
| 380 |
return VMMERR_SUCCESS;
|
| 381 |
}
|
| 382 |
|
| 383 |
vmmerr_t
|
| 384 |
read_linearaddr_w (ulong linear, void *data)
|
| 385 |
{
|
| 386 |
u64 pte;
|
| 387 |
bool us;
|
| 388 |
vmmerr_t err;
|
| 389 |
|
| 390 |
if ((linear & 0xFFF) == 0xFFF) {
|
| 391 |
RIE (read_linearaddr_b (linear, ((u8 *)data)));
|
| 392 |
RIE (read_linearaddr_b (linear + 1, ((u8 *)data + 1)));
|
| 393 |
return VMMERR_SUCCESS;
|
| 394 |
}
|
| 395 |
us = USER_MODE();
|
| 396 |
err = get_pte(linear, false, us, false /* FIXME */, &pte);
|
| 397 |
if (err) {
|
| 398 |
mmu_generate_pagefault(err, false, us, linear);
|
| 399 |
return err;
|
| 400 |
}
|
| 401 |
read_gphys_w ((pte & PTE_ADDR_MASK64) | (linear & 0xFFF), data,
|
| 402 |
msr_pte_to_cache_flag(pte));
|
| 403 |
return VMMERR_SUCCESS;
|
| 404 |
}
|
| 405 |
|
| 406 |
vmmerr_t
|
| 407 |
read_linearaddr_l (ulong linear, void *data)
|
| 408 |
{
|
| 409 |
u64 pte;
|
| 410 |
bool us;
|
| 411 |
vmmerr_t err;
|
| 412 |
|
| 413 |
if ((linear & 0xFFF) >= 0xFFD) {
|
| 414 |
RIE (read_linearaddr_w (linear, ((u8 *)data)));
|
| 415 |
RIE (read_linearaddr_w (linear + 2, ((u8 *)data + 2)));
|
| 416 |
return VMMERR_SUCCESS;
|
| 417 |
}
|
| 418 |
us = USER_MODE();
|
| 419 |
err = get_pte(linear, false, us, false /* FIXME */, &pte);
|
| 420 |
if (err) {
|
| 421 |
mmu_generate_pagefault(err, false, us, linear);
|
| 422 |
return err;
|
| 423 |
}
|
| 424 |
read_gphys_l ((pte & PTE_ADDR_MASK64) | (linear & 0xFFF), data,
|
| 425 |
msr_pte_to_cache_flag(pte));
|
| 426 |
return VMMERR_SUCCESS;
|
| 427 |
}
|
| 428 |
|
| 429 |
vmmerr_t
|
| 430 |
read_linearaddr_q (ulong linear, void *data)
|
| 431 |
{
|
| 432 |
u64 pte;
|
| 433 |
bool us;
|
| 434 |
vmmerr_t err;
|
| 435 |
|
| 436 |
if ((linear & 0xFFF) >= 0xFF9) {
|
| 437 |
RIE (read_linearaddr_l (linear, ((u8 *)data)));
|
| 438 |
RIE (read_linearaddr_l (linear + 4, ((u8 *)data + 4)));
|
| 439 |
return VMMERR_SUCCESS;
|
| 440 |
}
|
| 441 |
us = USER_MODE();
|
| 442 |
err = get_pte(linear, false, us, false /* FIXME */, &pte);
|
| 443 |
if (err) {
|
| 444 |
mmu_generate_pagefault(err, false, us, linear);
|
| 445 |
return err;
|
| 446 |
}
|
| 447 |
read_gphys_q ((pte & PTE_ADDR_MASK64) | (linear & 0xFFF), data,
|
| 448 |
msr_pte_to_cache_flag(pte));
|
| 449 |
return VMMERR_SUCCESS;
|
| 450 |
}
|
| 451 |
|
| 452 |
/* access a TSS during a task switch */
|
| 453 |
/* According to the manual, a processor uses contiguous physical addresses */
|
| 454 |
/* to access a TSS during a task switch */
|
| 455 |
vmmerr_t
|
| 456 |
read_linearaddr_tss (ulong linear, void *tss, uint len)
|
| 457 |
{
|
| 458 |
u64 pte;
|
| 459 |
void *p;
|
| 460 |
|
| 461 |
RIE (get_pte (linear, false, false, false, &pte));
|
| 462 |
p = mapmem_gphys ((pte & PTE_ADDR_MASK64) | (linear & 0xFFF), len, 0);
|
| 463 |
if (!p)
|
| 464 |
return VMMERR_NOMEM;
|
| 465 |
memcpy (tss, p, len);
|
| 466 |
unmapmem (p, len);
|
| 467 |
return VMMERR_SUCCESS;
|
| 468 |
}
|
| 469 |
|
| 470 |
vmmerr_t
|
| 471 |
write_linearaddr_tss (ulong linear, void *tss, uint len)
|
| 472 |
{
|
| 473 |
u64 pte;
|
| 474 |
void *p;
|
| 475 |
|
| 476 |
RIE (get_pte (linear, true, false, false, &pte));
|
| 477 |
p = mapmem_gphys ((pte & PTE_ADDR_MASK64) | (linear & 0xFFF), len,
|
| 478 |
MAPMEM_WRITE);
|
| 479 |
if (!p)
|
| 480 |
return VMMERR_NOMEM;
|
| 481 |
memcpy (p, tss, len);
|
| 482 |
unmapmem (p, len);
|
| 483 |
return VMMERR_SUCCESS;
|
| 484 |
}
|
| 485 |
|
| 486 |
void
|
| 487 |
mmu_generate_pagefault(vmmerr_t vmmerr, bool wr, bool us, ulong cr2)
|
| 488 |
{
|
| 489 |
u32 err = 0;
|
| 490 |
|
| 491 |
switch (vmmerr) {
|
| 492 |
case VMMERR_PAGE_NOT_PRESENT:
|
| 493 |
break;
|
| 494 |
case VMMERR_PAGE_NOT_ACCESSIBLE:
|
| 495 |
err = PAGEFAULT_ERR_P_BIT;
|
| 496 |
break;
|
| 497 |
case VMMERR_PAGE_BAD_RESERVED_BIT:
|
| 498 |
err = PAGEFAULT_ERR_P_BIT | PAGEFAULT_ERR_RSVD_BIT;
|
| 499 |
break;
|
| 500 |
case VMMERR_PAGE_NOT_EXECUTABLE:
|
| 501 |
err = PAGEFAULT_ERR_P_BIT | PAGEFAULT_ERR_ID_BIT;
|
| 502 |
break;
|
| 503 |
default:
|
| 504 |
panic("mmu_generate_pagefault: Unknown vmmerr. 0x%x", vmmerr);
|
| 505 |
}
|
| 506 |
if (wr) {
|
| 507 |
err |= PAGEFAULT_ERR_WR_BIT;
|
| 508 |
}
|
| 509 |
if (us) {
|
| 510 |
err |= PAGEFAULT_ERR_US_BIT;
|
| 511 |
}
|
| 512 |
current->vmctl.generate_pagefault (err, cr2);
|
| 513 |
}
|
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